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FEATURES
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LT3032 Dual 150mA Positive/Negative Low Noise Low Dropout Linear Regulator DESCRIPTION
The LT(R)3032 is a dual, low noise, positive and negative low dropout voltage linear regulator. Each regulator delivers up to 150mA with a typical 300mV dropout voltage. Each regulator's quiescent current is low (30A operating and <3A in shutdown) and well-controlled in dropout, making it an excellent choice for battery-powered circuits. Another key feature of the LT3032 is low output noise. Adding an external 10nF bypass capacitor to each regulator reduces output noise to 20VRMS/30VRMS over a 10Hz to 100kHz bandwidth. The LT3032 is stable with minimum output capacitors of 2.2F. The regulators do not require the addition of ESR as is common with other regulators. Internal protection circuitry includes reverse output protection, current limiting, and thermal limiting. Each regulator is offered as an adjustable output device with an output voltage down to the 1.22V reference voltages. The LT3032 is available in a unique low profile 14-lead 4mm x 3mm x 0.75mm DFN package with exposed backside pads for each regulator, allowing optimum thermal performance.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
Low Noise: 20VRMS (Positive) and 30VRMS (Negative) Low Quiescent Current: 30A/Channel Wide Input Voltage Range: 2.3V to 20V Output Current: 150mA Low Shutdown Current: <3A Total (Typical) Low Dropout Voltage: 300mV/Channel Adjustable Outputs from 1.22V to 20V No Protection Diodes Needed Stable with 2.2F Output Capacitors Stable with Ceramic, Tantalum or Aluminum Capacitors Starts into Reverse Output Voltage Current Limit and Thermal Limit Low Profile 14-Lead 4mm x 3mm x 0.75mm DFN Package
APPLICATIONS
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Battery-Powered Instruments Bipolar Power Supplies Low Noise Power Supplies
TYPICAL APPLICATION
Dual Polarity Low Noise 150mA Power Supply
INP 5.4V TO 20V <0.25V = OFF >2V = ON 10F SHDNP BYPP GND BYPN 10F -5.4V TO -20V INN SHDNN 249k ADJN 768k OUTN
3032 TA01
10Hz to 100kHz Output Noise
LT3032 OUTP 768k ADJP 249k 0.01F
5V OUT AT 150mA 20VRMS NOISE
OUTP 100V/DIV
20VRMS
10F
OUTN 100V/DIV 10F 0.01F -5V OUT AT -150mA 30VRMS NOISE 1mS/DIV
3032 TA02a
30VRMS
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LT3032 ABSOLUTE MAXIMUM RATINGS
(Note 1)
PIN CONFIGURATION
TOP VIEW OUTP ADJP BYPP GND GND INN OUTN 1 2 3 4 5 6 7 16 INN 15 GND 14 INP 13 NC 12 SHDNP 11 BYPN 10 SHDNN 9 INN 8 ADJN
INP Pin Voltage .......................................................20V INN Pin Voltage .......................................................20V OUTP Pin Voltage ...................................................20V OUTN Pin Voltage (Note 3) .....................................20V INP Pin to OUTP Pin Differential Voltage ................20V INN Pin to OUTN Pin Differential Voltage (Note 3)..........................................................-0.5V, 20V ADJP Pin Voltage ......................................................7V ADJN Pin Voltage (with Respect to INN Pin, Note 3) ..................-0.5V, 20V BYPP Pin Voltage ...................................................0.5V BYPN Pin Voltage (with Respect to INN Pin) .......................................20V SHDNP Pin Voltage .................................................20V SHDNN Pin Voltage (with Respect to INN Pin, Note 3) ..................-0.5V, 35V SHDNN Pin Voltage (with Respect to GND Pin) ..............................-20V, 15V Output Short-Circuit Duration .......................... Indefinite Operating Junction Temperature Range (Note 2) E, I Grades ............................................. -40C to 125C Storage Temperature Range .................. -65C to 150C
DEMA PACKAGE 14-LEAD (4mm 3mm) PLASTIC DFN TJMAX = 125C, JA = 30C/W TO 43C/W*, JC = 10C/W* *SEE APPLICATIONS INFORMATION FOR MORE DETAIL EXPOSED PAD (PIN 15) IS GND, MUST BE SOLDERED TO PINS 4, 5 ON PCB EXPOSED PAD (PIN 16) IS INN, MUST BE SOLDERED TO PINS 6, 9 ON PCB
ORDER INFORMATION
LEAD FREE FINISH LT3032EDE#PBF LT3032IDE#PBF LEAD BASED FINISH LT3032EDE LT3032IDE TAPE AND REEL LT3032EDE#TRPBF LT3032IDE#TRPBF TAPE AND REEL LT3032EDE#TR LT3032IDE#TR PART MARKING* 3032 3032 PART MARKING* 3032 3032 PACKAGE DESCRIPTION 14-Lead (4mm x 3mm) Plastic DFN 14-Lead (4mm x 3mm) Plastic DFN PACKAGE DESCRIPTION 14-Lead (4mm x 3mm) Plastic DFN 14-Lead (4mm x 3mm) Plastic DFN TEMPERATURE RANGE -40C to 125C -40C to 125C TEMPERATURE RANGE -40C to 125C -40C to 125C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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LT3032 ELECTRICAL CHARACTERISTICS
PARAMETER Minimum INP Operating Voltage Minimum INN Operating Voltage ADJP Pin Voltage (Notes 4, 5) ADJN Pin Voltage (Notes 4, 5, 10) Line Regulation (Note 5) Load Regulation (Note 5) CONDITIONS ILOAD = 150mA ILOAD = -150mA VINP = 2V, ILOAD = 1mA 2.3V VINP 20V, 1mA ILOAD 150mA VINN = -2V, ILOAD = -1mA -2.3V VINN -20V, -1mA ILOAD -150mA ADJP ADJN ADJP ADJN Dropout Voltage VINP = VOUTP(NOMINAL) (Notes 6, 7) ILOAD = 1mA ILOAD = 10mA ILOAD = 50mA ILOAD = 150mA Dropout Voltage VINN = VOUTN(NOMINAL) (Notes 6, 7) ILOAD = -1mA ILOAD = -10mA ILOAD = -50mA ILOAD = -150mA GND Pin Current VINP = VOUTP(NOMINAL), VINN = 0V (Notes 6, 8, 9) ILOAD = 0mA ILOAD = 1mA ILOAD = 10mA ILOAD = 50mA ILOAD = 150mA ILOAD = 0mA ILOAD = -1mA ILOAD = -10mA ILOAD = -50mA ILOAD = -150mA (Notes 5, 9) (Notes 5, 9) SHDNP SHDNP SHDNN SHDNN SHDNN SHDNN VOUTP = Off to On VOUTP = On to Off VOUTN = Off to On (Positive) VOUTN = Off to On (Negative) VOUTN = On to Off (Positive) VOUTN = On to Off (Negative)
l l l l l l l l l l l l l l l l l l l l l l l l l l l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C.
MIN -2.3 1.202 1.184 -1.238 -1.256 TYP 1.8 -1.6 1.22 1.22 -1.22 -1.22 1 1 -1.5 1.5 0.09 0.15 0.21 0.27 0.10 0.15 0.21 0.30 -25 -70 -350 -1.3 -4 30 85 300 0.75 2 30 -30 0.25 -2.8 0.25 -1 1 0.7 0.6 1.4 -1.9 1.4 -1.9 -65 -120 -500 -1.8 -7 70 180 600 1.5 5 100 -100 2 2 -0.25 1 4 0.20 0.27 1.238 1.256 -1.202 -1.184 6 12 -7 -15 7 15 0.20 0.27 MAX 2.3 UNITS V V V V V V mV mV mV mV mV mV V V V V V V V V A A A mA mA A A A mA mA nA nA V V V V V V A A
VINP = 2V to 20V, ILOAD = 1mA VINN = -2V to -20V, ILOAD = -1mA VINP = 2.3V, ILOAD = 1mA to 150mA VINP = 2.3V, ILOAD = 1mA to 150mA VINN = -2.3V, ILOAD = -1mA to 150mA VINN = -2.3V, ILOAD = -1mA to 150mA
GND Pin Current VINN = VOUTN(NOMINAL), VINP = 0V (Notes 6, 8, 9, 10)
ADJP Pin Bias Current ADJN Pin Bias Current Shutdown Threshold
SHDNP Pin Current (Note 9)
VSHDNP = 0V VSHDNP = 20V
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LT3032 ELECTRICAL CHARACTERISTICS
PARAMETER SHDNN Pin Current (Note 9) Quiescent Current in Shutdown Output Voltage Noise (10Hz to 100kHz) Ripple Rejection VRIPPLE = 0.5VP-P, fRIPPLE = 120Hz Current Limit CONDITIONS VSHDNN = 0V VSHDNN = 15V VSHDNN = -15V VINP = 6V, VSHDNP = 0V, VINN = 0V VINN = -6V, VSHDNN = 0V, VINP = 0V COUTP = 10F, CBYPP = 0.01F, ILOAD = 150mA COUTN = 10F, CBYPN = 0.01F, ILOAD = -150mA VINP to VOUTP = 1.5V (Average), ILOAD = 100mA VINN to VOUTN = -1.5V (Average), ILOAD = -100mA VINP = 7V, VOUTP = 0V VINN = -7V, VOUTN = 0V VINP = 2.3V, VOUTP = -0.1V VINN = -2.3V, VOUTN = 0.1V VINP = -20V, VOUTP = 0V VINN = 20V, VOUTN, VADJN, VSHDNN = Open Circuit VOUTP = VADJP = 1.22V, VINP < 1.22V 50 46
l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C.
MIN -1 6 -3 0.1 -3 20 30 68 60 400 350 170 170 -1 1 5 10 TYP MAX 1 15 -9 8 -10 UNITS A A A A A VRMS VRMS dB dB mA mA mA mA mA mA A
l l l l
INP Reverse Leakage Current INN Reverse Leakage Current Reverse Output Current (Notes 5, 11)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2. The LT3032 is tested and specified under pulse load conditions such that TJ TA. The LT3032E is 100% tested at TA = 25C. Performance of the LT3032E over the full -40C to 125C operating junction temperature range is assured by design, characterization, and correlation with statistical process controls. The LT3032I regulators are guaranteed over the full -40C to 125C operating junction temperature range. Note 3. Parasitic diodes exist internally between the INN pin and the OUTN, ADJN, and SHDNN pins. These pins cannot be pulled more than 0.5V below the INN pin during fault conditions, and must remain at a voltage more positive than the INN pin during operation. Note 4. Operating conditions are limited by maximum junction temperature. Specifications do not apply for all possible combinations of input voltages and output currents. When operating at maximum input voltages, the output current ranges must be limited. When operating at maximum output currents, the input voltage ranges must be limited. Note 5. The LT3032 is tested and specified for these conditions with the ADJP pin tied to the OUTP pin and the ADJN pin tied to the OUTN pin. Note 6. To satisfy requirements for minimum input voltage, the LT3032 is tested and specified for these conditions with an external resistor divider (two 250k resistors) from OUTP/OUTN to the corresponding ADJP/ADJN pin to give an output voltage of 2.44V. The external resistor divider adds a 5A DC load on the output.
Note 7. Dropout voltage is the minimum input-to-output voltage differential needed to maintain regulation at a specified output current. In dropout, output voltage equals: VINP/INN - VDROPOUT For lower output voltages, dropout voltage is limited by the minimum input voltage specification under some output voltage/load conditions; see curves for Minimum INN Voltage and Minimum INP Voltage in Typical Performance Characteristics. LTC is unable to guarantee Maximum Dropout Voltage specifications at 50mA and 150mA due to production test limitations with Kelvin-Sensing the package pins. Please consult the Typical Performance Characteristics for curves of Dropout Voltage as a function of Output Load Current and Temperature. Note 8. GND pin current is tested with VINP = VOUTP(NOMINAL) or VINN = VOUTN(NOMINAL) and a current source load. This means the device is tested while operating in its dropout region. This is the worst-case GND pin current. GND pin current decreases slightly at higher input voltages. Note 9. Positive current flow is into the pin. Negative current flow is out of the pin. Note 10. For input-to-output differential voltages from INN to OUTN greater than -7V, a -50A load is needed to maintain regulation. Note 11. Reverse output current is tested with the INP pin grounded and the OUTP pin forced to 1.22V. This current flows into the ADJP and OUTP pins and out the GND pin.
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LT3032 TYPICAL PERFORMANCE CHARACTERISTICS
INP-to-OUTP Typical Dropout Voltage
500 450 DROPOUT VOLTAGE (mV) DROPOUT VOLTAGE (mV) 400 350 300 250 200 150 100 50 0 0 20 40 60 80 100 120 140 160 LOAD CURRENT (mA)
3032 G01
INN-to-OUTN Typical Dropout Voltage
500 450 TJ = 125C DROPOUT VOLTAGE (mV) 400 350 300 250 200 150 100 50 0 0 -40 -80 -120 LOAD CURRENT (mA) -160
3032 G02
INP-to-OUTP Dropout Voltage
500 450 400 350 300 250 200 150 100 50 0 -50 -25 50 25 0 75 TEMPERATURE (C) 100 125 IL = 1mA IL = 50mA IL = 10mA IL = 150mA
TJ = 125C
TJ = 25C
TJ = 25C
3032 G03
INN-to-OUTN Dropout Voltage
500 450 QUIESCENT CURRENT (A) DROPOUT VOLTAGE (mV) 400 350 300 250 200 150 100 50 0 -50 -25 IL = 50mA IL = 10mA IL = 1mA IL = 150mA 40 35 30 25 20 15 10 5
INP Quiescent Current
VINP = 6V RL = 250k, IL = 5A QUIESCENT CURRENT (A) -50
INN Quiescent Current
VINN = -6V -45 RL = 250k IL = -5A -40 -35 -30 -25 -20 -15 -10 -5 VSHDNN = 0V -25 0 25 50 75 TEMPERATURE (C) 100 125 VSHDNN = VINN
VSHDNP = VINP
VSHDNP = 0V 50 25 0 75 TEMPERATURE (C) 100 125 0 -50 -25 0 25 50 75 100 125
0 -50
TEMPERATURE (C)
3032 G04 3032 G05
3032 G06
ADJP Pin Voltage
1.240 1.235 ADJP PIN VOLTAGE (V) 1.230 1.225 1.220 1.215 1.210 1.205 1.200 -50 -25 0 25 50 75 100 125 IL = 1mA -1.240 -1.235 ADJN PIN VOLTAGE (V) -1.230 -1.225 -1.220 -1.215 -1.210 -1.205
ADJN Pin Voltage
IL = -1mA INP QUIESCENT CURRENT (A) 30 25 20 15 10 5
INP Quiescent Current
VSHDNP = VINP
TJ = 25C RL = 250k
VSHDNP = 0V -1.200 -50 -25 TEMPERATURE (C)
3032 G07
0 25 50 75 TEMPERATURE (C)
100
125
0
0
2
4
6
8 10 12 14 16 18 20 INP VOLTAGE (V)
3032 G09
3032 G08
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LT3032 TYPICAL PERFORMANCE CHARACTERISTICS
INN Quiescent Current
-40 -35 INN QUIESCENT CURRENT (A) -30 -25 -20 -15 -10 -5 -0 0 VSHDNN = 0V TJ = 25C RL = 250k IL = -5A VSHDNN = VINN GND PIN CURRENT (mA) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 1 2 3 567 INP VOLTAGE (V) 4 8 9 10 0 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 INN VOLTAGE (V)
3032 G12 3032 G11
Positive Side GND Pin Current
-3.0 TJ = 25C VINP = VSHDNP *FOR VOUTP = 1.22V RL = 8.07 IL = 150mA* RL = 12.2 IL = 100mA* RL = 24.4 IL = 50mA* -2.5 GND PIN CURRENT (mA) -2.0 -1.5 -1.0 -0.5
Negative Side GND Pin Current
TJ = 25C; VSHDNN = VINN; *FOR VOUTN = -1.22V RL = 8.07 IL = -150mA* RL = 12.2 IL = -100mA* RL = 24.4 IL = -50mA* RL = 122 IL = -10mA*
-1 -2 -3 -4 -5 -6 -7 -8 -9 -10 INN VOLTAGE (V)
3032 G10
Positive Side GND Pin Current vs ILOAD
5.0 VINP = VOUTP(NOMINAL) + 1V 4.5 T = 25C J 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 20 60 80 100 120 140 160 POSITIVE LOAD CURRENT (mA)
3032 G13
Negative Side GND Pin Current vs ILOAD
-4.0 -3.5 SHDNP PIN THRESHOLD (V) GND PIN CURRENT (mA) -3.0 -2.5 -2.0 -1.5 TJ = 125C -1.0 -0.5 TJ = 25C TJ = -50C VINN = VOUTN(NOMINAL) - 1V 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -20 -40 -60 -80 -100 -120 -140 -160 NEGATIVE LOAD CURRENT (mA)
3032 G14
SHDNP Pin Threshold
IL = 1mA
GND PIN CURRENT (mA)
ON
OFF
40
0
0 -50
-25
50 25 0 75 TEMPERATURE (C)
100
125
3032 G15
SHDNN Pin Thresholds
2.5 2.0 SHDNN PIN VOLTAGE (V) 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 -50 -25 0 25 50 75 TEMPERATURE (C) ON OFF SHDNP PIN INPUT CURRENT (A) ON 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0
SHDNP Pin Input Current
1.6 SHDNP PIN INPUT CURRENT (A) 1.4 1.2 1.0 0.8 0.6 0.4 0.2
SHDNP Pin Input Current
VSHDNP = 20V
100
125
0
1
2
345678 SHDNP PIN VOLTAGE (V)
9
10
0 -50
-25
0
25
50
75
100
125
TEMPERATURE (C)
3032 G17 3032 G18
3032 G16
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LT3032 TYPICAL PERFORMANCE CHARACTERISTICS
SHDNN Pin Input Current
10 8 SHDNN PIN INPUT CURRENT (A) 6 4 2 0 -2 -4 -6 -8 -10 -10 -8 -6 -4 -2 0 2 4 6 SHDNN PIN VOLTAGE (V) 8 10 SHDNN PIN INPUT CURRENT (A) TJ = 25C POSITIVE CURRENT FLOWS INTO THE PIN 12 9 6 VSHDNN = 15V 3 0 -3 -6 -9 -50 VSHDNN = -15V VINN = -15V POSITIVE CURRENT FLOWS INTO THE PIN
SHDNN Pin Input Current
140 120 100 80 60 40 20
ADJP Pin Bias Current
ADJP PIN BIAS CURRENT (nA)
-25
0 25 50 75 TEMPERATURE (C)
100
125
0 -50
-25
50 25 0 75 TEMPERATURE (C)
100
125
3032 G19
3032 G20 3032 G21
ADJN Pin Bias Current
-70 -60 -50 -40 -30 -20 -10 0 -50 POSITIVE SIDE CURRENT LIMIT (mA) 500 450 400 350 300 250 200 150 100 50 0
Positive Side Current Limit
500 POSITIVE SIDE CURRENT LIMIT (mA) VOUTP = 0V 450 400 350 300 250 200 150 100 50
Positive Side Current Limit
VINP = 7V VOUTP = 0V
ADJN PIN BIAS CURRENT (nA)
-25
0 25 50 75 TEMPERATURE (C)
100
125
0
7 4 3 2 5 6 1 INP-TO-OUTP DIFFERENTIAL VOLTAGE (V)
3032 G23
0 -50
-25
50 25 0 75 TEMPERATURE (C)
100
125
3032 G22 3032 G24
Negative Side Current Limit
-600 NEGATIVE SIDE CURRENT LIMIT (mA) NEGATIVE SIDE CURRENT LIMIT (mA) VOUTN = 100mV -500 -400 -300 -200 -100 0 -600 -500 -400 -300 -200 -100
Negative Side Current Limit
100 REVERSE OUTP PIN CURRENT (mA) VINN = -7V VOUTN = 0V 90 80 70 60 50 40 30 20 10 0
Reverse OUTP Pin Current
TJ = 25C, VINP = 0V CURRENT FLOWS INTO OUTP PIN VOUTP = VADJP
0
-4 -8 -12 -16 -20 INN-TO-OUTN DIFFERENTIAL VOLTAGE (V)
3032 G25
0 -50
-25
0 25 50 75 TEMPERATURE (C)
100
125
0
1
2
345678 OUTP PIN VOLTAGE (V)
9
10
3032 G26 3032 G27
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LT3032 TYPICAL PERFORMANCE CHARACTERISTICS
Reverse OUTP Pin Current
30 REVERSE OUTP PIN CURRENT (A) 25 20 15 10 5 0 -50 INP-TO-OUTP RIPPLE REJECTION (dB) VINP = 0V VOUTP = 1.22V 80 70 60 50 40 30 20 10 0 -25 50 25 0 75 TEMPERATURE (C) 100 125 10 100 1k 10k FREQUENCY (Hz) 100k 1M
3032 G29
INP-to-OUTP Ripple Rejection
80 INP-TO-OUTP RIPPLE REJECTION (dB) 70 60 50 40 30 20 10 0
INP-to-OUTP Ripple Rejection
CBYPP = 0.01F
CBYPP = 1000pF CBYPP = 100pF
COUTP = 10F
IL = 150mA VINP = VOUTP(NOMINAL) + 1.5V + 50mVRMS RIPPLE CBYPP = 0
COUTP = 2.2F
IL = 150mA VINP = VOUTP(NOMINAL) + 1.5V + 50mVRMS RIPPLE COUTP = 10F 10 100 1k 10k FREQUENCY (Hz) 100k 1M
3032 G30
3032 G28
INN-to-OUTN Ripple Rejection
80 INN-TO-OUTN RIPPLE REJECTION (dB) 70 60 50 40 30 20 10 COUTN = 1F 0 10 100 1k 10k FREQUENCY (Hz) 100k 1M
3032 G31
INP-to-OUTP Ripple Rejection
68 66 64 62 60 58 56 54 52 -50 VINP = VOUTP(NOMINAL) + 1.5V + 0.5VP-P RIPPLE AT f = 120Hz IL = 150mA -25 0 25 50 75 100 125 INN-TO-OUTN RIPPLE REJECTION (dB) INP-TO-OUTP RIPPLE REJECTION (dB) 60 58 56 54 52 50 48 46
INN-to-OUTN Ripple Rejection
VINN = VOUTN(NOMINAL) - 1.5V + 0.5VP-P RIPPLE AT f = 120Hz IL = -150mA
IL = -150mA VINN = VOUTN(NOMINAL) - 1.5V + 50mVRMS RIPPLE CBYPN = 0
COUTN = 10F
44 -50
-25
TEMPERATURE (C)
3032 G32
0 25 50 75 TEMPERATURE (C)
100
125
3032 G33
Minimum INP Pin Voltage
2.50 2.25 MINIMUM INP PIN VOLTAGE (V) 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 -50 -25 50 25 0 75 TEMPERATURE (C) 100 125 IL = 1mA VOUTP = 1.22V MINIMUM INN PIN VOLTAGE (V) -2.5 -2.0 -3.0
Minimum INN Pin Voltage
0 POSITIVE LOAD REGULATION (mV) -2 -4 -6 -8 -10 -12 -14 -16 -18
Positive Load Regulation
IL = 150mA
IL = -150mA -1.5 -1.0 -0.5 0 -50 IL = -1mA NOTE: THE SHDNN PIN THRESHOLD MUST BE MET TO ENSURE DEVICE OPERATION -25 0 25 50 75 TEMPERATURE (C) 100 125
-20 -50
VINP = VOUTP(NOMINAL) +1V IL = 1mA TO 150mA -25 0 25 50 75 TEMPERATURE (C) 100 125
3032 G35 3032 G34
3032 G36
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LT3032 TYPICAL PERFORMANCE CHARACTERISTICS
Negative Load Regulation
10 NEGATIVE LOAD REGULATION (mV) 9 8 7 6 5 4 3 2 1 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125 VINN = VOUTN(NOMINAL) -1V IL = -1mA TO -150mA OUTP NOISE SPECTRAL DENSITY (V/Hz) 10
OUTP Noise Spectral Density
OUTN NOISE SPECTRAL DENSITY (V/Hz) COUTP = 10F IL = 150mA CBYPP = 0.01F 10
OUTN Noise Spectral Density
CBYPN = 1000pF CBYPN = 100pF 1 CBYPN = 0
CBYPP = 1000pF CBYPP = 100pF
1
0.1
0.1
CBYPN = 0.01F COUTN = 10F IL = -150mA VOUTN = 5V VOUTN = VADJN 1k 10k FREQUENCY (Hz) 100k
3032 G39
0.01 10
VOUTP = 5V VOUTP = VADJP 100 1k 10k FREQUENCY (Hz) 100k
3032 G38
0.01 10 100
3032 G37
OUTP RMS Noise vs Bypass Capacitor
160 140 OUTP RMS NOISE (VRMS) 120 100 80 60 40 20 0 10 100 CBYPP (pF)
3032 G40
OUTP RMS Noise vs Load Current (10Hz to 100kHz)
160 140 COUTP = 10F CBYPP = 0 CBYPP = 0.01F VOUTP = 5V OUTN RMS NOISE (VRMS) 120 140 OUTP RMS NOISE (VRMS) 120 100 80 60 40 20 1k 10k 0 0.01 0.1 VOUTP = 5V VOUTP = VADJP 10 100 1 LOAD CURRENT (mA) 1k
3032 G41
OUTN RMS Noise vs Bypass Capacitor
COUTN = 10F IL = -150mA f = 10Hz TO 100kHz
VOUTP = 5V
COUTP = 10F IL = 150mA f = 10Hz TO 100kHz
VOUTN = 5V 100 80 60 40 20 0 10 100
VOUTP = VADJP
VOUTP = VADJP
VOUTN = VADJN
1k CBYPN (pF)
10k
3032 G42
OUTN RMS Noise vs Load Current (10Hz to 100kHz)
140 COUTN = 10F CBYPN = 0 120 CBYPN = 0.01F OUTN RMS NOISE (VRMS) 100 80 60 40 20 0 -0.01 VOUTN = VADJN VOUTP 100V/DIV VOUTN = 5V
OUTP 10Hz to 100kHz Output Noise CBYPP = 0
OUTP 10Hz to 100kHz Output Noise CBYPP = 0.01F
VOUTP 100V/DIV
VOUTN = 5V VOUTN = VADJN COUTP = 10F IL = 150mA VOUTP = 5V 1ms/DIV
3032 G44
COUTP = 10F IL = 150mA VOUTP = 5V
1ms/DIV
3032 G45
-0.1
-1 -10 -100 LOAD CURRENT (mA)
-1k
3032 G43
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LT3032 TYPICAL PERFORMANCE CHARACTERISTICS
OUTN, 10Hz to 100kHz Output Noise, CBYPN = 0 OUTN, 10Hz to 100kHz Output Noise, CBYPN = 0.01F
VOUTN 200V/DIV
VOUTN 100V/DIV
COUTN = 10F ILOAD = -150mA VOUTN = -5V
1ms/DIV
3032 G46
COUTN = 10F ILOAD = -150mA VOUTN = -5V
1ms/DIV
3032 G47
OUTP Transient Response CBYPP = 0
0.3 0.2 OUTP VOLTAGE DEVIATION (V) 0.1 0 -0.1 -0.2 -0.3 LOAD CURRENT (mA) LOAD CURRENT (mA) 150 100 50 0 0 400 800 1200 TIME (s) 1600 2000
3032 G48
OUTP Transient Response CBYPP = 0.01F
0.04 OUTP VOLTAGE DEVIATION (V) 0.02 0 -0.02 -0.04 VOUTP = 5V VINP = 6V CINP = 10F COUTP = 10F
VOUTP = 5V VINP = 6V CINP = 10F COUTP = 10F
150 100 50 0 0 40 80 120 TIME (s) 160 200
3032 G49
OUTN Transient Response CBYPN = 0
0.2 OUTN VOLTAGE DEVIATION (V) 0.1 0 -0.1 -0.2 0 LOAD CURRENT (mA) -50 -100 -150 0 100 200 300 400 500 600 700 800 900 1k TIME (s)
3032 G50
OUTN Transient Response CBYPN = 0.01F
0.06 0.04 OUTN VOLTAGE DEVIATION (V) 0.02 0 VOUTN = -5V VINN = -6V CINN = 10F COUTN = 10F
VOUTN = -5V VINN = -6V CINN = 10F COUTN = 10F
-0.02 -0.04 -0.06
LOAD CURRENT (mA)
0 -50 -100 -150 0 50 100 150 200 250 300 350 400 450 500 TIME (s)
3032 G51
3032f
10
LT3032 PIN FUNCTIONS
OUTP (Pin 1): Positive Output. This output supplies power to the positive side load. A minimum output capacitor of 2.2F is required to prevent oscillations. Larger output capacitors are required for applications with large transient loads to limit peak voltage transients. See the Applications Information section for more information on output capacitance, bypass capacitance, and reverse output characteristics. ADJP (Pin 2): Positive Adjust. This is the input to the positive side error amplifier. This pin is internally clamped to 7V. It has a typical bias current of 30nA which flows into the pin (see curve of ADJP Pin Bias Current vs Temperature in the Typical Performance Characteristics). The ADJP pin voltage is 1.22V referenced to ground and the output voltage range is 1.22V to 20V. BYPP (Pin 3): Positive Bypass. The BYPP pin is used to bypass the reference of the positive side regulator to achieve low noise performance. The BYPP pin is clamped internally to 0.6V (one VBE). A small capacitor from OUTP to this pin will bypass the reference to lower the output voltage noise. A maximum value of 0.01F is used for reducing output voltage noise to a typical 20VRMS over the 10Hz to 100kHz bandwidth. If not used, this pin must be left unconnected. GND (Pins 4, 5, Exposed Pad Pin 15): Ground. One of the DFN's exposed backside pads (Pin 15) is an electrical connection to ground. To ensure proper electrical and thermal performance, solder Pin 15 to the PCB's ground and tie directly to Pins 4 and 5. Connect the bottom of the positive and negative output voltage setting resistor dividers directly to Pins 4 and 5 for optimum load regulation performance. INN(Pin 6, 9, Exposed Pad Pin 16): Negative Input. The DFN package's second exposed backside pad (Pin 16) is an electrical connection to INN. To ensure proper electrical and thermal performance, solder Pin 16 to the PCB's negative input supply and tie directly to Pins 6 and 9. Power is supplied to the negative side of the LT3032 through the INN pins. A bypass capacitor is required on this pin if it is more than six inches away from the main input filter capacitor. In general, the output impedance of a battery rises with frequency, so it is advisable to include a bypass capacitor in battery-powered circuits. A bypass capacitor in the range of 1F to 10F is sufficient. OUTN(Pin 7): Negative Output. This output supplies power to the negative side load. A minimum output capacitor of 1F is required to prevent oscillations. Larger output capacitors are required for applications with large transient loads to limit peak voltage transients. A parasitic diode exists between OUTN and INN; OUTN can not be pulled more negative than INN during normal operation, or more than 0.5V below INN during a fault condition. See the Applications Information section for more information on output capacitance and bypass capacitors. ADJN(Pin 8): Negative Adjust. This is the input to the negative side error amplifier. The ADJN pin has a typical bias current of 30nA that flows out of the pin. The ADJN pin voltage is -1.22V referenced to ground, and the output voltage range is -1.22V to -20V. A parasitic diode exists between ADJN and INN. The ADJN pin cannot be pulled more negative than INN during normal operation, or more than 0.5V below INN during a fault condition. SHDNN(Pin 10): Negative Shutdown. The SHDNN pin puts the negative side into a low power shutdown state. The SHDNN pin is referenced to ground for regulator control, allowing the negative side to be driven by either positive or negative logic. The negative output will be off if the SHDNN pin is within 0.8V(typical) of ground. Pulling the SHDNN pin more than -1.9V or +1.6V(typical) will turn the negative output on. The SHDNN pin can be driven by 5V logic or open-collector logic with a pull-up resistor. The pull-up resistor is required to supply the pull-up current of the open-collector device, normally several microamperes, and the SHDNN pin current, typically 3A out of the pin (for negative logic) or 6A into the pin (for positive logic). If unused, the SHDNN pin must be connected to INN. The negative output will be shut down if the SHDNN pin is open circuit. A parasitic diode exists between SHDNN and INN, the SHDNN pin cannot be pulled more negative than INN during normal operation, or more than 0.5V below INN during a fault condition. BYPN(Pin 11): Negative Bypass. The BYPN pin is used to bypass the reference of the negative side regulator to achieve low noise performance. A small capacitor from OUTN to this pin will bypass the reference to lower the output voltage noise. A maximum value of 0.01F is used for reducing output voltage noise to a typical 30VRMS
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11
LT3032 PIN FUNCTIONS
over the 10Hz to 100kHz bandwidth. If not used, this pin must be left unconnected. SHDNP (Pin 12): Positive Shutdown. The SHDNP pin puts the positive side into a low power shutdown state. The positive output will be off when the SHDNP pin is pulled below 0.8V(typical). The SHDNP pin can be driven by 5V logic or open-collector logic with a pull-up resistor. The pull-up resistor is required to supply the pull-up current of the open-collector device, normally several microamperes, and the SHDNP pin current, typically 1A into the pin. If unused, the SHDNP pin must be connected to INP The . positive output will be shut down if the SHDNP pin is open circuit. The SHDNP pin can be tied directly to the SHDNN pin and both pins driven directly by positive logic for a single point control of both outputs. NC (Pin 13): No Connect. The No Connect pin has no connection to internal circuitry and may be tied to INP , GND, INN, SHDNP, SHDNN, OUTP OUTN, floated, or tied , to any other point. INP(Pin 14): Positive Input. Power is supplied to the positive side of the LT3032 through the INP pin. A bypass capacitor is required on this pin if it is more than six inches away from the main input filter capacitor. In general, the output impedance of a battery rises with frequency, so it is advisable to include a bypass capacitor in batterypowered circuits. A bypass capacitor in the range of 1F to 10F is sufficient.
3032f
12
LT3032 APPLICATIONS INFORMATION
The LT3032 is a dual 150mA positive and negative low noise low dropout linear regulator with micropower quiescent current and shutdown. It supplies 150mA at a dropout of 300mV. Output voltage noise can be lowered on the positive side to 20VRMS and to 30VRMS on the negative side over the 10Hz to 100kHz bandwidth with the addition of 0.01F reference bypass capacitors. Additionally, the reference bypass capacitors improve transient response, lowering the settling time for transient load conditions. Quiescent current is 20A for the positive side and -30A for the negative side, typically dropping to less than 3A total in shutdown. In addition to the low quiescent current, the LT3032 incorporates several protection features which make it ideal for use in battery-powered systems. If the load is common mode between the two outputs, it does not matter which output starts first; either output can be pulled to the opposing side of ground and the regulator will still start and operate. Setting Output Voltage The LT3032 has output voltage ranges of 1.22V to 20V for the positive side and -1.22V to -20V for the negative side. The output voltages are set by the ratio of two external resistor dividers as shown in Figure 1. The LT3032 servos the outputs to maintain the voltages at the ADJP and ADJN pins to 1.22V and -1.22V, respectively. The current in the bottom resistor of each divider (R1P or R1N) is equal to 1.22V/R1 and the current in the top resistor (R2P or R2N) is equal to the current in the bottom resistor plus the respective ADJP/ADJN pin bias current. The bias current for ADJP and ADJN is 30nA at 25C, flowing into the pin for ADJP and flowing out of the pin for ADJN. The output voltages can then be calculated using the formulas shown in Figure 1. The value of R1P or R1N should be less than 250k to minimize errors in the resultant output voltage caused by the ADJP/ADJN pin bias current. Note that in shutdown the respective output is turned off and the divider current will be zero. Curves of ADJP Pin Voltage, ADJN Pin Voltage, ADJP Pin Bias Current, and ADJN Pin Bias Current (all vs Temperature) appear in the Typical Performance Characteristics.
OUTP LT3032 ADJP R1P GND R1N ADJN R2N OUTN
3032 F01
R2P
+
VOUTP
R 2P (R 2P) + I VOUTP = 1.22 V 1+ R1P ADJP VADJP = 1.22 V
(
)
IADJP = 30nA at 25C OUTPUT RANGE = 1.22 V TO 20 V R 2N (R 2N) + I VOUTN = -1.22 V 1+ R1N ADJN VADJN = -1.22 V .
(
)
+
VOUTN
IADJN = -30nA at 25C OUTPUT RANGE = -1.22 V TO - 20 V
Figure 1. Setting Output Voltages
The LT3032 is tested and specified with the ADJP/ADJN pin tied to the respective OUTP/OUTN pin and a 5A DC load (unless otherwise specified) for an output voltage of 1.22V. Specifications for output voltages greater than this will be proportional to 1.22V; (VOUT/1.22V). For example, load regulation for an output current change of 1mA to 150mA is -2mV typical at VOUTN = -1.22V. At VOUTN = -12V, load regulation is: (-12V/-1.22V)*(-2mV) = -19.6mV Bypass Capacitors and Low Noise Performance The LT3032 provides reasonable noise performance without reference bypass capacitors from OUTP/OUTN to the corresponding BYPP/BYPN pin. Using the LT3032 with the addition of reference bypass capacitors lowers output voltage noise. Good quality low leakage capacitors are recommended. These capacitors bypass the internal references for the positive and negative sides of the LT3032, providing low frequency noise poles. The noise poles provided by the bypass capacitors decrease the output voltage noise to as low as 20VRMS for the positive side and 30VRMS for the negative side with the use of 0.01F bypass capacitors. The BYPP pin and BYPN pin are high impedance nodes and leakage into or out of these pins affects the reference voltage. The BYPP pin operates at approximately 74mV
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13
LT3032 APPLICATIONS INFORMATION
at 25C during normal operation where the BYPN pin operates at approximately -60mV. DC leakages on the order of 1A into or out of these pins can throw off the internal reference by 20% or more. Output Capacitance and Transient Response The LT3032 requires output capacitors for stability. It is designed to be stable with most low ESR capacitors (typically ceramic, tantalum or low ESR electrolytic). A minimum output capacitor of 2.2F with an ESR of 3 or less is recommended to prevent oscillations on each output. The LT3032 is a micropower device and output transient response is a function of output capacitance. Larger values of output capacitance decrease peak deviations and provide improved transient response for larger load current changes. Additional capacitors, used to decouple individual components powered by the LT3032, increase the effective output capacitor value. When using bypass capacitors (for low noise operation), larger values of output capacitors are needed. For 100pF of bypass capacitance, 3.3F of output capacitance is recommended. With a 330pF bypass capacitor or larger, a 4.7F output capacitor is recommended. The shaded region of Figure 2 defines the range over which the LT3032 is stable. The minimum ESR needed is defined by the amount of bypass capacitance used, while the maximum ESR is 3. These requirements are applicable to both the positive and negative linear regulator.
4.0 3.5 3.0 STABLE REGION 2.5 ESR () 2.0 1.5 1.0 0.5 0 1 3 2 4 5 6 7 8 9 10 OUTPUT CAPACITANCE (F)
1762 F02
Give extra consideration to the use of ceramic capacitors. Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior across temperature and applied voltage. The most common dielectrics used are specified with EIA temperature characteristic codes of Z5U, Y5V, X5R and X7R. The Z5U and Y5V dielectrics are good for providing high capacitances in a small package, but they tend to have strong voltage and temperature coefficients as shown in Figures 3 and 4. When used with a 5V regulator, a 16V 10F Y5V capacitor can exhibit an effective value as low as 1F to 2F for the DC bias voltage applied and over the operating temperature range. The X5R and X7R dielectrics result in more stable characteristics and are more suitable for use as the output capacitor. The X7R type has better stability across temperature, while the X5R is less expensive and is available in higher values. Care still must be exercised when using X5R and X7R capacitors. The X5R and X7R codes only specify operating temperature range and maximum capacitance change over temperature. Capacitance change due to DC bias with X5R and X7R capacitors is better than Y5V and Z5U capacitors, but can still be significant enough to drop capacitor values below appropriate levels. Capacitor DC bias characteristics tend to improve as component case size increases, but expected capacitance at operating voltage should be verified in situ for a given application. Voltage and temperature coefficients are not the only sources of problems. Some ceramic capacitors have a piezoelectric response. A piezoelectric device generates voltage across its terminals due to mechanical stress. In a ceramic capacitor, the stress can be induced by vibrations in the system or thermal transients. Tapping on the ceramic bypass capacitor with a pencil generated the noise shown in Figure 5. Similar vibration induced behavior can masquerade as increased output voltage noise.
CBYP = 0 CBYP = 100pF CBYP = 330pF CBYP 3300pF
Figure 2. Stability
3032f
14
LT3032 APPLICATIONS INFORMATION
20 0 CHANGE IN VALUE (%) X5R -20 -40 -60 Y5V -80 -100 BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10F
Stability and Input Capacitance Low ESR, ceramic input bypass capacitors are acceptable for applications without long input leads. However, applications connecting a power supply to an LT3032's circuit's INP/INN and GND pins with long input wires combined with low ESR, ceramic input capacitors are prone to voltage spikes, reliability concerns and applicationspecific board oscillations. The input wire inductance found in many battery-powered applications, combined with the low ESR ceramic input capacitor, forms a high-Q LC resonant tank circuit. In some instances this resonant frequency beats against the output current dependent LDO bandwidth and interferes with proper operation. Simple circuit modifications/solutions are then required. This behavior is not indicative of LT3032 instability, but is a common ceramic input bypass capacitor application issue. The self-inductance, or isolated inductance, of a wire is directly proportional to its length. Wire diameter is not a major factor on its self-inductance. For example, the selfinductance of a 2-AWG isolated wire (diameter = 0.26") is about half the self-inductance of a 30-AWG wire (diameter = 0.01"). One foot of 30-AWG wire has about 465nH of self-inductance.
125
0
2
4
8 6 10 12 DC BIAS VOLTAGE (V)
14
16
3032 F03
Figure 3. Ceramic Capacitor DC Bias Characteristics
40 20 CHANGE IN VALUE (%) 0 -20 -40 -60 -80 BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10F 50 25 75 0 TEMPERATURE (C) 100 Y5V X5R
-100 -50 -25
3032 F04
Figure 4. Ceramic Capacitor Temperature Characteristics
OUTPUT SET TO 5V
3032 F05
Figure 5. Noise Resulting From Tapping on a Ceramic Capacitor
One of two ways reduces a wire's self-inductance. One method divides the current flowing towards the LT3032 between two parallel conductors. In this case, the farther apart the wires are from each other, the more the selfinductance is reduced; up to a 50% reduction when placed a few inches apart. Splitting the wires basically connects two equal inductors in parallel, but placing them in close proximity gives the wires mutual inductance adding to the self-inductance. The second and most effective way to reduce overall inductance is to place both forward and return current conductors (the input and GND wires) in very close proximity. Two 30-AWG wires separated by only 0.02", used as forward- and return- current conductors, reduce the overall self-inductance to approximately onefifth that of a single isolated wire.
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15
LT3032 APPLICATIONS INFORMATION
If wiring modifications are not permissible for the applications, including series resistance between the power supply and the input of the LT3032 also stabilizes the application. As little as 0.1 to 0.5, often less, is effective in damping the LC resonance. If the added impedance between the power supply and the input is unacceptable, adding ESR to the input capacitor also provides the necessary damping of the LC resonance. However, the required ESR is generally higher than the series impedance required. Thermal Considerations The power handling capability of the device is limited by the maximum rated junction temperature (125C). The power dissipated by the device is made up of the following components: 1. Output current of each side multiplied by the respective input/output voltage differential: (IOUT)(VIN to VOUT), and 2. GND pin current for each side multiplied by its input voltage: (IGND)(VIN) The GND pin current of each side is found by examining the GND Pin Current curves in the Typical Performance Characteristics. Total power dissipation equals the sum for both channels of the components listed above. The LT3032 has internal thermal limiting designed to protect each side of the regulator during overload conditions. For continuous normal conditions, the maximum junction temperature rating of 125C must not be exceeded. It is important to give careful consideration to all sources of thermal resistance from junction to ambient. Additional heat sources mounted nearby must also be considered. The LT3032 is a surface mount device and heat sinking is accomplished by using the heat spreading capabilities of the PC board and its copper traces. Copper board stiffeners and plated through-holes can also be used to spread the heat generated by power devices. Note that the Exposed Pads (Pins 15 and 16) are electrically connected to ground (GND) and the negative input (INN) respectively. The following table lists thermal resistance as a function of copper area on a fixed board size. All measurements were taken in still air on a 4-layer FR-4 board with 1oz solid internal planes and 2oz external trace planes with a total finished board thickness of 1.6mm.
Table 3. DE Package, 14-Lead DFN
COPPER AREA TOPSIDE* 2500mm2 1000mm2 225mm2 100mm2 BACKSIDE 2500mm2 2500mm2 2500mm2 2500mm2 BOARD AREA 2500mm2 2500mm2 2500mm2 2500mm2 THERMAL RESISTANCE (JUNCTION-TO-AMBIENT) 32C/W 33C/W 38C/W 43C/W
*Device is mounted on topside
For further information on thermal resistance and using thermal information, refer to JEDEC standard JESD51, notably JESD51-12. PCB layers, copper weight, board layout and thermal vias affect the resultant thermal resistance. This table provides thermal resistance numbers for best-case 4-layer boards with 1oz internal and 2oz external copper. Modern, multilayer PCBs may not be able to achieve quite the same level performance as found in this table.
3032f
16
LT3032 APPLICATIONS INFORMATION
Calculating Junction Temperature Example: Given a positive output voltage of 3.3V, a positive input voltage of 4V to 6V, output current range from 10mA to 150mA, negative output voltage of -3.3V, negative input voltage of -5V to -6V, a negative output current of -100mA, and a maximum ambient temperature of 50C, what will the maximum junction temperature be for a 2500mm2 board with topside copper of 1000mm2? The power in each side equals: PSIDE = (VIN(MAX) - VOUT)(IOUT(MAX))+(VIN(MAX)*IGND) where, IOUTP(MAX) = 150mA VINP(MAX) = 6V IGND at (IOUTP = 150mA, VINP = 6V) = 3.7mA IOUTN(MAX) = -100mA VINN(MAX) = -6V IGND at (IOUTN = -100mA, VINN = -6V) = -1.5mA The total power equals: PTOTAL = PPOSITIVE + PNEGATIVE So, PPOSITIVE = 150mA(6V - 3.3V) + 3.7mA(6V) = 0.43W P NEGATIVE = -100mA(-6V+3.3V)-1.5mA(-6V) = 0.28W PTOTAL = 0.43W + 0.28W = 0.71W Junction Temperature equals: TJ = TA + PTOTAL * JA (using tables) TJ = 50C + 0.71W * 33C/W = 73.4C In this case, the junction temperature is below the maximum rating, ensuring reliable operation. If an input is left open circuit or grounded, the corresponding output can be pulled to its opposing polarity by as much as 20V. The output will act like an open circuit; no current will flow into or out of the pin. If the input is powered by a voltage source, the output will source the short-circuit current and will protect itself by thermal limiting. In this case, grounding the respective SHDNP/ SHDNN pin will turn off that side of the LT3032 and stop the output from sourcing current. The ADJP pin can be pulled above or below ground by 7V without damage to the device. If the input is left open circuit or grounded, the ADJP pin acts like an open circuit when pulled below ground and like a large resistor (typically 100k) in series with a diode when pulled above ground.
3032f
Protection Features The LT3032 incorporates several protection features that make it ideal for use in battery-powered circuits. In addition to the normal protection features associated with monolithic regulators, such as current limiting and thermal limiting, the LT3032 is protected against reverse input voltages and reverse output voltages on both channels. Current limit protection and thermal overload protection protect the device against current overload conditions at the outputs of the part. For normal operation, the junction temperature should not be allowed to exceed 125C. The positive input of the LT3032 withstands 20V reverse voltage. The negative input also withstands reverse voltage, but the negative input may not be more than 0.5V (one VBE) higher than the OUTN and SHDNN pins. This provides protection against batteries that are plugged in backwards. The outputs of the LT3032 can be pulled to opposing voltages without damaging the part. The outputs may be pulled to the opposing polarity with a load that is common mode between the two and one regulator starts before the other; in this condition, it does not matter which regulator started first. Both sides are capable of having the output pulled to the opposing polarity and both will still start and operate.
17
LT3032 APPLICATIONS INFORMATION
In situations where the ADJP pin is connected to a resistor divider that would pull the ADJP pin above its 7V clamp voltage if the output is pulled high, the ADJP pin input current must be limited to less than 5mA. For example, a resistor divider is used to provide a 1.5V output from the 1.22V reference and the output is forced to 20V. The top resistor of the divider must be chosen to limit the current into the ADJP pin to less than 5mA when the ADJP pin is at 7V. The 13V difference between OUTP and ADJP divided by the 5mA maximum current into the ADJP pin yields a minimum top resistor value of 2.6k. In circuits where a backup battery is required on the positive output, several different input/output conditions can occur. The output voltage may be held up while the input is either pulled to ground, pulled to some intermediate voltage or is left open circuit. Current flow back into OUTP follows the curve shown in Figure 6.
100 REVERSE OUTP PIN CURRENT ( A) 90 80 70 60 50 40 30 20 10 0 0 1 2 345678 OUTP PIN VOLTAGE (V) 9 10 TJ = 25 C, VINP = 0V CURRENT FLOWS INTO OUTP PIN VOUTP = VADJP
Like many IC power regulators, the negative side of the LT3032 has safe operating area (SOA) protection. The safe operating area protection activates when the differential voltage between INN and OUTN is greater than -7V. The SOA protection decreases current limit as a function of the voltage differential between INN and OUTN and keeps the power transistor inside a safe operating region for all values of forward input-to-output voltage. The protection is designed to provide some output current at all values of INN to OUTN differential voltage up to the Absolute Maximum Rating. A 50A load is required to maintain regulation for INN to OUTN differential voltages greater than -7V. When power to the negative side is first turned on, as the input voltage rises, OUTN follows INN, allowing the regulator to start into very heavy loads. During start-up, as the INN voltage is rising, the differential voltage between INN and OUTN is small, allowing the negative side to supply large output currents. With a high INN voltage, a problem can occur wherein removal of an output short will not allow the output voltage to fully recover. Other regulators, such as the LT1175, LT1964, and LT3080 also exhibit this phenomenon, so it is not unique to the LT3032. The problem occurs with a heavy output load when the INN voltage is high and the OUTN voltage is low. Common situations are immediately after the removal of a shortcircuit or when the SHDNN pin is pulled high after the INN pin has already been turned on. The load line for such a load may intersect the output current curve at two points. If this happens, there are two stable operating points for the negative side of the LT3032. With this double intersection, the INN supply may need to be cycled down to zero and brought up again to make OUTN recover.
3032 F06
Figure 6. Reverse Output Current
If the INP pin is forced below the OUTP pin or the OUTP pin is pulled above the INP pin, input current typically drops to less than 2A. This can happen if the device is connected to a discharged (low voltage) bat-tery and the output is held up by a backup battery or a second regulator circuit. The state of the SHDNP pin has no effect on the reverse output current if OUTP is pulled above INP.
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18
LT3032 PACKAGE DESCRIPTION
DE14MA Package 14-Lead Plastic DFN, Multichip (4mm 3mm)
(Reference LTC DWG #05-08-1731 Rev O)
1.78 0.05
0.70 0.05
3.50 0.05 1.65 0.05 2.10 0.05
0.10 TYP 0.51 TYP 1.07 0.05
1.65 0.05
PACKAGE OUTLINE 0.25 0.05 0.50 BSC 3.00 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 0.10 (2 SIDES) R = 0.05 TYP
R = 0.115 TYP 8
1.78 0.10 14
3.00 0.10 (2 SIDES) PIN 1 TOP MARK (SEE NOTE 6) 0.200 REF 0.75 0.05
1.65 0.10
1.07 0.10
0.10 TYP 0.51 TYP
1.65 0.10
0.40 0.10
7
1 0.25 0.05 0.50 BSC 3.00 REF
PIN 1 NOTCH R = 0.20 OR 0.25 45 CHAMFER
(DE14MA) DFN 1106 REV O
0.00 - 0.05
BOTTOM VIEW--EXPOSED PAD
NOTE: 1. DRAWING PROPOSED IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
3032f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LT3032 TYPICAL APPLICATION
5V to 15V Tracking Supply
5.5V TO 20V 5V TO 15V AT 150mA 10F INP LT3032 BYPP OFF ON SHDNP ADJP GND SHDNN 250k ADJN BYPN 0.01F -5.5V TO -20V OUTN
3032 TA02
OUTP 0.01F 536k
95.3k
536k
10F -5V TO -15V AT -150mA
RELATED PARTS
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Dual 100mA/500mA, Low Noise, VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, VDO = 0.32V, IQ = 60A, ISD < 1A; DFN and Micropower LDO with Independent Inputs TSSOP-16E Packages Dual 500mA/500mA, Low Dropout, Low Noise, Micropower Linear Regulator Low Noise: 20VRMS (10Hz to 100kHz), Low Quiescent Current: 55A per Channel Wide Input Voltage Range: 1.8V to 20V (Common or Independent Input Supply) Adjustable Output: 1.215V Reference, Very Low Quiescent Current in Shutdown: <1A per Channel Stable with 3.3F Minimum Output Capacitor, Thermally Enhanced 16-Lead MSOP and 16-Lead (4mm x 3mm) DFN Packages
LT3082
200mA, Parallelable, Single Resistor, Low Wide Input Voltage Range: 1.2V to 40V Low Value Input/Output Capacitors Required: Dropout Linear Regulator 0.22F, Single Resistor Sets Output Voltage Initial Set Pin Current Accuracy: 1%, Low Output Noise: 40VRMS (10Hz to 100kHz) Reverse-Battery Protection, Reverse-Current Protection 8-Lead SOT-23, 3-Lead SOT-223 and 8-Lead 3mm x 3mm DFN Packages
ThinSOT is a trademark of Linear Technology Corporation.
3032f
20 Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
LT 0210 * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2010

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